The present invention relates generally to the field of integrated circuits. More particularly, the invention relates to a phase locked loop circuit having reduced sensitivity to noise. The invention is used to improve the synchronization of the internal timing or clock signals within an integrated circuit such as a synchronous dynamic random access memory (SDRAM) to external timing or clock signals. The invention is also used in multi-rate high speed transmission buffers.
Most digital logic implemented on integrated circuits is clocked synchronous sequential logic. In electronic devices such as synchronous dynamic random access memory circuits (SDRAMs), microprocessors, digital signal processors, and so forth, the processing, storage, and retrieval of information is coordinated with a clock signal. The speed and stability of the clock signal determines to a large extent the data rate at which a circuit can function. Many high-speed integrated circuit devices, such as SDRAMs, microprocessors, etc., rely upon clock signals to control the flow of commands, data, addresses, etc., into, through and out of the devices.
A continual demand exists for devices with higher data rates; consequently, circuit designers have begun to focus on ways to increase the frequency of the clock signal. In SDRAMs, it is desirable to have the data output from the memory synchronized with the system clock that also serves the microprocessor. The delay between a rising edge of the system clock (external to the SDRAM) and the appearance of valid data at the output of the memory circuit is known as the clock access time of the memory. A goal of memory circuit designers is to minimize clock access time as well as to increase clock frequency.
One of the obstacles to reducing clock access time has been clock skew, that is, the delay time between the externally supplied system clock signal and the signal that is routed to the memory""s output circuitry. An external system clock is generally received with an input buffer and then further shaped and redriven to the internal circuitry by an internal buffer. The time delay of the input buffer and the internal buffer will skew the internal clock from the external clock. This clock skew will cause signals that are to be transferred from the integrated circuit to be out of synchronization with the external system clock. This skew in the clock signal internal to the integrated circuit is furthered by the delays incurred in the signal passing through the clock input buffer and driver and through any associated resistive-capacitive circuit elements. One solution to the problem of clock skew is the use of a synchronous mirror delay. One problem with the synchronous mirror delay is that, although these type of delays require fewer clock cycles to achieve lock of an external clock signal and an internal clock signal, the synchronous mirror delay has a limited operational frequency range. Another solution to the problem of clock skew is the use of a phase locked loop (PLL) that has a greater operational frequency range. A PLL is capable of tracking phase as well as frequency of the clock signal. A typical PLL includes a voltage control oscillator (VCO). The VCO outputs a signal with frequency corresponding to a voltage. Because of the relatively large bandwidth of PLLs, oftentimes they are operated on the lower frequencies of the bandwidth. It has been found that the voltage signals controlling the VCOs are sensitive to noise, particularly at the lower frequencies. At lower voltage levels, voltage noise (or jitter) has a proportionally greater effect on the signal. Therefore, it is desirable to reduce the amount of noise or jitter on the control voltage of the VCO. At the same time, it is desired to maintain the locking function of the PLL.
The present invention solves the aforementioned problems, and decreases the amount of noise or jitter on the control voltage of a voltage controlled oscillator.
In one aspect of the invention, a method of decreasing voltage controlled oscillator noise susceptibility and a phase locked loop is disclosed. The method includes providing a phased lock loop (PLL) having a voltage controlled oscillator (VCO) and controlled by a control voltage VCTRL and having a VCO frequency. A desired voltage range is defined from a minimum voltage to a maximum voltage and a desired frequency range is defined from a minimum frequency to a maximum frequency. The method includes comparing the VCO frequency to the minimum frequency and the maximum frequency, and comparing VCTRL to the minimum voltage and the maximum voltage, and selectively adjusting a gain of the VCO under specific VCTRL voltage and VCO frequency conditions as determined by the comparison steps.
In another aspect of the invention, a method of adjusting noise sensitivity in a phase locked loop includes providing a phase locked loop having a voltage controlled oscillator (VCO) controlled by a control voltage VCTRL and having a VCO frequency. The method includes decreasing a gain of the VCO when the VCTRL is less than a defined voltage minimum and when the VCO frequency is not less than a defined frequency minimum. The method also includes increasing a gain of the VCO when the VCTRL is greater than a defined voltage maximum and when the VCO frequency is not greater than a defined frequency maximum.
In another aspect of the invention, a phase locked loop circuit is disclosed and includes a voltage controlled oscillator for generating a VCO frequency controlled by a control voltage VCTRL. The circuit includes a frequency comparator to compare a reference frequency with the VCO frequency and output a frequency comparison result signal. A phase and frequency detector is disclosed with a charge pump connected to the PFD and outputting the control voltage VCTRL. A filter is included to filter a target frequency range from the control voltage VCTRL, and a voltage comparator is connected to the charge pump for comparing the control voltage to a voltage maximum and a voltage minimum. The voltage comparator outputs a voltage comparison result signal. Control logic connected to the voltage comparator and the frequency comparator selectively adjusts VCO gain based on the voltage comparison result signal and the frequency comparison result signal.